EDA Tools used at Various stages of SoC Design Flow
NOTE & REQUEST: We request VLSICore members to send EDA tools irrespective of the EDA Vendor that you work or known.
SoC Flow
- Specification
- Layout & Library Development
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* CosmosLE/SE [Synopsys]
* Virtuoso [Cadence]
* ICstation [Mentor Graphics]
* L-Edit [Tanner]
* MicroWind [MicroWind]
* LASI [University of Berkeley]
* Magic []
* Electric []
- Library Characterization
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* Star-MTB [Synopsys]
* NanoChar [Synopsys]
* NLG
* FRONTEND Flow
- RTL Coding
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* vi/emacs Editor [unix]
* Cadence Composer [Cadence]
- Scan Insertion
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* DFT Compiler [Synopsys]
* DFT Advisor [Mentor Graphics]
- Formal Verification
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* VCS [Synopsys]
* Formality [Synopsys]
* Conformal LEC [Cadence]
* Verplex [Verplex]
* FormalPro [Mentor Graphics]
- Simulation
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* VCS - Vera [Synopsys]
* NC-Verilog / Verilog XL [Cadence]
* finsim [Fintronics]
* Event Simulation - MTI VHDL Model Sim [Mentor]
* Event Simulation - VSS {VHDL} [Synopsys]
* Event Simulation - Verilog - Verilog XL [Cadence]
* Event Simulation - Verilog - MTI Model Sim Plus [Mentor]
* Event Simulation - Verilog - VCS [Synopsys]
* Veriloger []
- Synthesis
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* RTL Compiler [Cadence]
* Design Compiler [Synopsys]
* DC Expert for ASIC [Synopsys]
* Blast RTL [Magma]
* Exempler for FPGA
* Leornado Spectrum [Mentor]
- FPGA Synthesis
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* Quartus []
* Xilinx [Xilinx]
* DC-FPGA [Synopsys]
* Precision Synthesis [Mentor Graphics]
- ATPG and Tests
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* Tetra Max [Synopsys]
* DFT Compiler [Synopsys]
* SynTest
* Test Compiler [Synopsys]
* Testbench [IBM]
* Vera / NTB [Synopsys]
* Fast Scan [Mentor Graphics]
- Logic BIST
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* LBIST Architect [Mentor Graphics]
- Memory BIST
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* MBIST Architect [Mentor Graphics]
- Boundary Scan Insertion
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* BSD Architect [Mentor Graphics]
- STA - Timing Analysis
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* PrimeTime [Synopsys]
* Showtime [Sequence]
* Design Time [Synopsys]
* CoolTime [Sequence]
* Pearl [Cadence]
- Transistor Level Analysis & Verification
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* PathMill [Synopsys]
* BACKEND Flow
- Hierarchical Design Planning
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* JupiterXT [Synopsys]
* PKS [Cadence]
* First Encounter (FE) [Cadence]
* BlastPlan [Magma]
- Place & Route
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* Apollo/Astro [Synopsys]
* IC Compiler [Synopsys]
* Physical Compiler [Synopsys]
* Gate/Silicon Ensemble [Cadence]
* Nano Encounter [Cadence]
* SoC Encounter [Cadence]
* Blast Fusion [Magma]
* Montery Dolphin
* AutoCells [Mentor Graphics]
- Clock Tree Synthesis (CTS)
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* CTGen [Cadence]
* Clock Tree Compiler (CTC) [Synopsys]
* Astro/Apollo/ ICC [Synopsys]
- Physical Verification [DRC/LVS/ERC/ OPC]
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* Calibre [Mentor]
* Hercules [Synopsys]
* Assura [Cadence]
* Dracula [Cadence]
* Vampire [Cadence]
* Diva [Cadence]
* Mojave [Mojave]
- Parasitics/RC Extraction
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* Star-RCXT [Synopsys]
* Arcadia [Synopsys]
* Columbus Turbo [Sequence : RC Extraction]
* Columbus Gold [Sequence : RLC Extraction]
* Fire&Ice [earlier called as Simplex]
* CalibreRC [Mentor]
*
- Power Analysis
- RTL/Gate Power Analysis
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* PowerTheater Analyst [Sequence : predicts rtl and netlist power] * earlier known as Sente Wattwatcher
* Power Compiler [Synopsys]
* PrimePower [Synopsys]
* AstroRail - Static [Synopsys]
* PrimeRail - Dynamic & Static [Synopsys]
* Power Compiler [Synopsys]
- Signal Integrity / Crosstalk
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* PrimeTime SI [Synopsys]
* AstroXtalk [Synopsys]
* CeltIC [Cadence]
* Physical Studio [Sequence]
- Glitch Analysis
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* Physical Studio [Sequence]
* PTSI/PrimePower [Synopsys]
- Electro Migration (EM Analysis)
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* Prime-Rail [Synopsys]
* AstroXtalk (EM) [Synopsys]
- Analog/Mixed Signal Simulation [Tr. Level]
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* HSPICE [Synopsys]
* Nanosim [Synopsys]
* HSIM [Synopsys]
* Spectre [Cadence]
* X-Eldo [Mentor]
* Win-SPICE [Free Tool]
* Columbus RF [Sequence : RLC Extraction - Analog]
* B2SPICE [Beige Bag]
- Pattern Conversion to Hardware Test
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* TSSI Advantest Wavebridge
* TDS6000 [IBM]
- IC Packaging
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* Foundry Flow
- OPC/FAB Process
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* Tauras [Synopsys]
* CATS [Synopsys]
* Calibre OPC / RET / MDP [Mentor Graphics]
- Mask Verification
- Tape-Out (Post Silicon]
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